FIG. 4 is the block diagram showing a priority order judging device according to a background art. In FIG. 4, each channel 1, 1, . . . outputs a priority order code signal 2 (2a to 2c), 2 (2a to 2c), . . . (refer to FIG. 5). Each decoder 3, 3, . . . decodes the priority order code signal 2, 2, . . . to output it as a priority decode signal 4 (4a to 4h), 4 (4a to 4h), . . . (refer to FIG. 5). A judgement circuit 5 judges the priority order of the priority order decode signal 4, 4, . . . and outputs the highest priority order signal as a judged priority order signal 6 (6a to 6h). An encoder 7 encodes the judged priority order signal 6 and outputs it as judgement result code signals 8, 9 and 10.
The decoders 3, judgement circuit 5 and encoders 7 may be those generally used, examples of which are shown in FIGS. 5 to 7. These circuits are generally used, so a detailed description for them is omitted. As seen from FIG. 5, the decoder 3 is constructed of three inverters 2A.sub.1 to 2A.sub.3 and eight NOR gates 3B.sub.1 to 3B.sub.8. As seen from FIG. 6, the judgement circuit 5 is constructed of eight NOR gates 5A.sub.1 to 5A.sub.8. The NOR gate 5A.sub.1 is inputted with signals 4a, 4a, . . . of the decode signals 4, 4, . . . . The NOR gate 5A.sub.2 is inputted with signals 4b, 4b, . . . of the decode signals 4, 4, . . . . Similarly, the last NOR gate 5A.sub.8 is inputted with decode signals 4h, 4h, . . . of the decode signals 4, 4, . . . . The NOR gates 5A.sub.1 to 5A.sub.8 output judged priority order signals 6a to 6h, respectively. As seen from FIG. 7, the encoder 7 is constructed of an inverter 7A, six NOR gates 7B.sub.1 to 7B.sub.6, and the NOR gates 7C.sub.1 to 7C.sub.3.
The order judging device according in the background art has been constructed heretofore as described above. It is therefore necessary to provide the decoder 3 for each channel, and the encoder 7 for outputting the judgement result code signals 8, 9 and 10, resulting in a large circuit scale of the device. Further, the priority order decode signals 4, 4, . . . outputted from the decoders 3, 3, . . . and the judged priority order signals 6 outputted from the judgement circuit 5, are decode signals so that a number of signal lines for the signal transfer between circuits becomes necessary. A number of signal lines require a large space. Furthermore, the judgement circuit 5 itself becomes complicated because the highest priority order signal should be found among a number of priority order decode signals inputted from a number of signal lines.